A Dynamic Random Access Memory (DRAM) has memory arrays consisting of a number of memory cells. In a conventional DRAM each memory cell (sometimes referred to as a memory bit) consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line (sometimes referred to as a bit line) of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to an access line (sometimes referred to as a word line) of the memory device. The transistor thus acts as a gate between the digit line and the capacitor. A second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the word line for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the polarity of the voltage across the capacitor is positive or negative, represents either a logic high or a logic low value.
Typically, particular word and column select lines are activated to access selected memory cells. “Access” typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells typically involves the use of a sense circuit, such as an amplifier, to detect whether the voltage level stored in the memory cell represents a binary one or a binary zero.
At least two different types of DRAM arrays are currently used; a folded digit line architecture and an open digit line architecture. FIG. 1 is a simplified circuit diagram of a folded digit line architecture. Memory cells include an access transistor 10 coupled to a storage capacitor 12. The gates of the access transistors 10 are coupled to word lines 16. Sense amplifier circuits are placed at the edge of each array and connect to both true digit lines 14 and complement digit lines 18 coming from a single array. The memory cells are accessed by activating the proper word lines 16. For read cycles, the sense amplifier then senses a difference in voltage between the digit line pair (14, 18) to determine a programmed value for the cell.
FIG. 2 is a simplified circuit diagram of an open digit line architecture. Memory cells include an access transistor 10 coupled to a storage capacitor 12. The gates of the access transistors 10 are coupled to word lines 16. In an open digit line architecture, the digit line pairs (14, 18) are in opposing memory arrays and the sense amplifiers are positioned between the digit line pairs (14, 18). Thus, the true digit line 14 is on one side of a sense amplifier and the complement digit line 18 is on the othr side of a sense amplifier. In contrast, digit line pairs (14, 18) in a folded digit line architecture (FIG. 1) are formed side by side in the same array. As a result, a sense amplifier for sensing a digit line pair is formed on one side of the digit line pair.
Each architecture has its advantages and disadvantages. One disadvantage of an open digit architecture is that while the core arrays are fully utilized, the end arrays use only half of the available digit lines, which wastes valuable semiconductor real estate. As used herein, the terms “core array” and “end array” are used to distinguish between the arrays but not necessarily to indicate a particular functionality.
Layouts to reduce this wasted space have been proposed. As an example, in one proposal, the end arrays are made at half the width of the core arrays and the digit lines traverse the array then wrap back and traverse an adjacent digit line location. This arrangement creates a single digit line in the end arrays that occupies two digit line locations that are each half as long, which results in a close matching of the capacitive loading of the full length digit lines of the fully utilized array that shares sense amplifiers with the end array. Unfortunately, in this arrangement the wrapped digit lines in the end arrays may still perform differently and have different noise characteristics from the straight digit lines in the core arrays.
The inventors have appreciated that there is a need for methods, apparatuses, and systems using open digit architectures that can make use of the extra digit lines in full size end arrays.